The invention relates to an analog/digital converter for successive approximation conversion of an analog input signal into a digital output signal at an increased conversion rate. Analog/digital converters are electronic circuits that convert an analog input signal into a digital output signal. In the successive approximation method, the data bits of the digital output signal are successively determined one after the other in successive approximation steps. To such an end, the analog/digital converter is provided with a comparator, a digital/analog converter DAC, a successive approximation register SAR, and a logic circuit. The successive approximation method first involves setting the most significant bit MSB and then using the digital/analog converter DAC to ascertain the associated value of an analog voltage. If the input analog voltage to be converted is greater than the ascertained output analog voltage of the digital/analog converter DAC, then the set bit remains set and, in the converse case, it is reset. The next less significant bit is then set and the digital/analog converter DAC is used to generate the associated analog output voltage from the corresponding digital value. The analog output voltage so formed is compared with the-analog input-voltage that is to be converted, and the comparator is then used to decide whether or not the set bit can remain set. The method is continued in this manner until all the bits of the binary-coded digital/analog converter have been ascertained successively. In the case of such analog/digital converters based on the prior art, the conversion rate depends primarily on the speed of the comparator. The comparator has a multistage configuration. The comparator generally contains at least one linear input stage for linear amplification of an analog input signal using a relatively low gain and also at least one output stage with a relatively high gain.
The time limits substantially determining the conversion rate of the analog/digital converter are prescribed firstly by the recovery time of the comparator following overdriving of the linear input stage and secondly by the minimum switching time of the comparator at a low drive level.
Because the data bits of the digitally converted value are ascertained successively, the conversion rate is lower than that of a parallel converter, and an increase in speed or an increase in the conversion rate is particularly desirable for an analog/digital converter using successive approximation.
It is accordingly an object of the invention to provide an analog/digital converter for successive approximation conversion of an analog input signal into a digital output signal and method for converting an analog input signal into a digital output signal that overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that performs the successive approximation conversion at an increased conversion rate.
With the foregoing and other objects in view, there is provided, in accordance with the invention, an analog/digital converter for successive approximation conversion of an analog input signal into a digital output signal, including a clocked successive approximation register buffer storing a digital value, a digital/analog converter converting the digital value buffer-stored in the register to form an analog comparison signal, the digital/analog converter connected to the register and outputting the analog comparison signal, at least one comparator having at least one linear input stage connected to the digital/analog converter and an output stage, the at least one comparator comparing the analog input signal with the analog comparison signal, outputting a comparator output signal for setting the register and at least one overdrive indicator signal, and indicating with the at least one overdrive indicator signal an overdriving of the at least one linear input stage, an acceleration circuit connecting the at least one comparator to the register, the acceleration circuit outputting a switchable clock signal to the register based upon the at least one overdrive indicator signal.
The idea on which the inventive analog/digital converter is based is that of detecting the overdriving of the linear input stages of the comparator and of clocking the successive approximation register on the basis thereof.
In such case, the overdriving does not absolutely need to be detected very accurately.
In accordance with another feature of the invention, the linear input stage contains a differential amplifier circuit and an overdrive detection circuit for detecting the overdriving of the differential amplifier.
In accordance with a further feature of the invention, the at least one linear input stage is a plurality of linear input stages and each of the linear input stages respectively have a differential amplifier circuit and an overdrive detection circuit for detecting an overdriving of the differential amplifier circuit.
In accordance with an added feature of the invention, the overdrive detection circuit is a window discriminator.
The input side of the acceleration circuit is preferably connected to a clock generator.
In accordance with an additional feature of the invention, the acceleration circuit has a pulse generator, downstream of whose output side there are a first delay element for delaying the generated pulse by the recovery time of the comparator and a second delay element for delaying the generated pulse by the maximum decision time of the comparator, the signal outputs of the two delay elements being connected to a controlled switching device that connects the signal outputs of the delay elements to the successive approximation register based upon the overdrive indicator signal.
In accordance with yet another feature of the invention, the switching device is preferably a multiplexer.
In accordance with yet a further feature of the invention, the pulse generator is preferably a flip-flop, in particular, a D-type flip-flop. In such case, the output of the multiplexer is preferably coupled to the flip-flop.
In accordance with yet an added feature of the invention, the multiplexer has an output, the pulse generator is a D-type flip-flop, and the output of the multiplexer is fed back to the D-type flip-flop.
In accordance with yet an additional feature of the invention, there is provided a clock generator connected to the acceleration circuit, the pulse generator, the first delay element, and the second delay element being clocked synchronously by the clock generator.
In accordance with again another feature of the invention, there is provided a read register connected to the register for reading a digitized final value from the register.
In accordance with again a further feature of the invention, the overdrive detection circuit preferably detects the level and the arithmetic sign of the overdriving of the differential amplifier.
In accordance with again an added feature of the invention, the clock signal can be switched over by the acceleration circuit between a first clock signal having a minimum clock period and a second clock signal having a maximum clock period.
In accordance with again an additional feature of the invention, the minimum clock period corresponds to the recovery time of the comparator, and the maximum clock period corresponds to the;maximum required decision time of the comparator.
In accordance with still another feature of the invention, the minimum clock period can be set externally as the delay of the first delay element, and the maximum clock period can be set externally as the delay of the two delay elements.
With the objects of the invention in view, there is also provided a method for converting an analog input signal into a digital output signal, having the following steps:
(a) the analog input signal is compared with an analog comparison signal, which corresponds to a digital value buffer-stored in a clocked successive approximation register, by a comparator;
(b) a comparator output signal is formed based upon the comparison result to set the buffer-stored digital value in the successive approximation register;
(c) detecting if a linear input stage of the comparator is overdriven; and
(d) a clock signal for the clocked successive approximation register is switched over to a first clock signal having a minimum clock period if overdriving is detected and to a second clock signal having a maximum clock period if no overdriving is detected.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an analog/digital converter, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.